參數(shù)資料
型號： MC68HC05F8FU
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PQFP64
封裝： PLASTIC, QFP-64
文件頁數(shù)： 62/126頁
文件大小： 1084K
代理商： MC68HC05F8FU
MOTOROLA
5-4
MC68HC05F8
INTERRUPTS
5
5.1
Hardware Controlled Sequences
The following three functions are not strictly interrupts, however, they are tied very closely to the
interrupts. These functions are RESET, STOP, WAIT.
1) RESET
The RESET input pin causes the program to go to its starting
address. This address is specied by the contents of memory
locations $FFFE and $FFFF. The interrupt mask of the condition
code register is also set. Most parts of the MCU is congured to
some known state as described in Table 4-1.
2) STOP
The STOP instruction causes the oscillator to be turned off and
the processor “sleeps” until an external interrupt (IRQ), keyboard
interrupt, or RESET occurs. See Section 11 on Low Power
Modes.
3) WAIT
The WAIT instruction causes all processor clocks to stop, but
leaves the Timer A, Timer B, MANCD and SPI clocks running.
This “rest” state of the processor can be exited by RESET, an
external interrupt (IRQ), keyboard interrupt, Timer or SPI
interrupt. There are no special wait vectors for these individual
interrupts. See Section 11 on Low Power Modes.
5.2
Software Interrupt (SWI)
The software interrupt is an executable instruction. The action of the SWI instruction is similar to
the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the
condition code register. The service routine address is specied by the contents of memory
location $FFFC and $FFFD.
5.3
External Interrupts (IRQ1 & IRQ2)
The external interrupts IRQ1 and IRQ2 can be software congured for “negative-edge” or
“negative-edge and level” sensitive triggering.
When the signal of the external interrupt pin, IRQ1 or IRQ2, satises the condition selected by the
INTN1 and INTN2 bit in the System Option register (bits 4 & 3 of address $35), an external
interrupt occurs, and the appropriate INTF ag will be set. The actual processor interrupt is
generated only if the interrupt mask bit of the condition code register is also cleared. When the
interrupt is recognized, the current state of the processor is pushed onto the stack and the
interrupt mask bit in the condition code register is set. This masks further interrupts until the
present one is serviced. The service routine address is specied by the contents of $FFFA &
$FFFB for both IRQ1 & IRQ2. After servicing the interrupt, ags are cleared by writing a logic “0”
to the corresponding ag; otherwise the CPU will keep servicing the interrupt.
TPG
38
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For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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