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| 型號(hào)： | MC68HC05F8FU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 95/126頁(yè) |
| 文件大?。?/td> | 1084K |
| 代理商： | MC68HC05F8FU |
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MOTOROLA
7-6
MC68HC05F8
SERIAL PERIPHERAL INTERFACE
7
DCOL - Data Collision
This is a read only status bit which indicates that an invalid access to the data register has been
made. This can occur any time after the rst falling edge of SCK and before SPIF is set. A read or
write of the data register during this time will result in invalid data being transmitted or received.
DCOL is cleared by reading the status register with SPIF set followed by a read or write of the data
register. If the last part of the clearing sequence is done after another transmission has been
started, DCOL will be set again. Reset also clears this bit.
7.4.3
Serial Peripheral Data Register (SPDR)
The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only
a write to this register will initiate transmission/reception of another byte and this will only occur in
the master device. A slave device writing to its data I/O register will not initiate a transmission. At
the completion of transmitting a byte of data, the SPIF status bit is set in both the master and slave
devices. A write or read of the serial peripheral data I/O register, after accessing the serial
peripheral status register with SPIF set, will clear SPIF.
During the clock cycle that the SPIF bit is being set, a copy of the received data byte in the shift
register is being moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read. During an overrun condition, when the master device has sent
several bytes of data and the slave device has not internally responded to clear the rst SPIF, only
the rst byte is contained in the receive buffer at any time. The rst SPIF must be cleared by the
time a second transfer of data from the shift register to the read buffer is initiated or an overrun
condition will exist.
A write to the serial peripheral data I/O register is not buffered and places data directly into the
shift register for transmission.
The ability to access the serial peripheral data I/O register is limited when a transmission is taking
place. It is important to read the discussion dening the DCOL and SPIF status bits to understand
the limits on using the serial peripheral data I/O register.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$12
TPG
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