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| 型號(hào)： | MC68HC05F8FU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 86/126頁(yè) |
| 文件大?。?/td> | 1084K |
| 代理商： | MC68HC05F8FU |
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MOTOROLA
6-14
MC68HC05F8
TIMERS
6
6.3.2
COP System Enable and Operation
A watchdog timer enable (WDTE) bit in the WDCSR is used to enable the COP watchdog system.
Its default value is “0” at reset (watchdog disabled).
Writing a “1” to this bit will load the watchdog timer counter with the initial value selected by
WDT0 & WDT1 bits and activate the watchdog timer clock. When the watchdog timer counter
reaches zero, a watchdog time-out signal is generated to reset the MCU with WDTOF set.
Once the watchdog is enabled, it cannot be disabled by software; writing a “0” to the WDTE bit has
no effect.
6.3.3
Disable COP Function in Stop or Wait Mode
A kill watchdog timer (KWDT) bit is provided in the WDCSR to optionally disable and reset the
watchdog timer when the STOP or WAIT instruction is executed. This allows the CPU to go into
an extended sleep or Wait mode without watchdog timer resets. This feature is not enabled if the
KWDT bit is set to “0”.
The KWDT bit permits a “STOP” or “WAIT” instruction to disable the Watchdog Timer. To do so,
KWDT must be written to a logic “1” on the rst write to the WDCSR after a reset. However, this
rst write only enables the “kill” feature. A second write of a logic “0” to KWDT must be performed
to engage the “kill” feature. After the second write, the execution of a STOP or WAIT instruction
will reset the Watchdog Timer and disable the COP watchdog system. Two specic writes are
required for this feature to prevent accidental engagement by a single spurious write.
The watchdog counter resumes counting when the MCU exits Stop or Wait mode.
6.3.4
Watchdog Timer Control Status Register (WDCSR)
WDTE - Watchdog Timer Enable/Disable
1 (set)
–
Watchdog timer enabled.
0 (clear) –
Watchdog timer disabled.
The default for the watchdog timer at reset is disabled. Once enabled by writing a logic “1” to this
bit, it cannot be disabled by software. Writing a logic “0” have no effect to this bit.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$36
WDTE
KWDT
WDTOF
WDT1
WDT0
000- --00
TPG
60
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For More Information On This Product,
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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