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| 型號(hào)： | MC68HC05F8FU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 81/126頁(yè) |
| 文件大小： | 1084K |
| 代理商： | MC68HC05F8FU |
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MOTOROLA
6-10
MC68HC05F8
TIMERS
6
6.2
TIMER B - RELOADABLE TIMER
The Reloadable Timer is similar to the Free-running Timer, with the following differences:
The 16-bit timer counter is automatically reloaded from the preset timer registers upon
underow occurs.
There is no input capture function, i.e. no TCAP.
There is no output compare function, i.e. no TCMP.
The Reloadable Timer is convenient for generating periodic interrupts without the aid of software.
In addition, the timer counter value can be read in a similar way to timer A.
6.2.1
Functional Description
See Figure 6-6 for a block diagram of the Reloadable Timer.
The timer B is driven by a clock which is derived from E divided by 4, 8, 16 or 32. In the Control
Register, two bits TCSB0 and TCSB1 are used to select the divider for the prescaler, TBOIE is an
interrupt enable bit, TMEB is a Timer B enable bit which will inhibit the driving clock when it is clear.
Upon reset, the Control Register is cleared, Timer B is disabled, Timer B interrupt is inhibited, the
free running counter and the Preset Register are all congured to $FFFF.
The preset register should be written with proper value before enable the Timer B. A low to high
transition of the TMBE bit loads the timer counter with the content in the preset register and
activates the driving clock, then the free running counter starts to count down, when it rolls over
from $0001 to $0000 an interrupt is generated with timer B underow ag set if the TBOIE is set,
meanwhile a “l(fā)oad” signal is produced to reload the counter with the content of the preset register,
thus interruption will occur periodically.
6.2.2
Resolution and Maximum Period
When a 3.579MHz crystal is used, the timer resolution and its maximum period are shown in
Table 6-2 Reloadable Timer Resolution and Maximum Period
TCSB1
TCSB0
FREQUENCY
RESOLUTION
MAX. PERIOD PRESET $FFFF
0
E/4
2.25
s
147ms
0
1
E/8
4.5
s
294ms
1
0
E/16
9
s
588ms
1
E/32
18
s
1176ms
Where E = internal bus clock
TPG
56
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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