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參數(shù)資料
| 型號(hào)： | MC68HC05JB3JP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 136/148頁 |
| 文件大?。?/td> | 1600K |
| 代理商： | MC68HC05JB3JP |
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GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
UNIVERSAL SERIAL BUS MODULE
MC68HC05JB3
10-20
REV 1
Software must also set RX0E bit to one to enable the next data packet recep-
tion. If RXD0F bit is not cleared, a NAK handshake will be returned in the next
OUT transaction.
Reset clears this bit. Writing a logic 0 to RXD0F has no effect.
1 =
Receive on Endpoint 0 has occurred.
0 =
Receive on Endpoint 0 has not occurred.
RSTF — USB Reset Flag
This read only bit is set when a valid reset signal state is detected on the D+
and D– lines. This reset detection will also generate an internal reset signal to
reset the CPU and other peripherals including the USB module. This bit is
cleared by writing a logic 1 to the RSTFR bit in the UCR2 register. This bit is
cleared by a POR reset.
SUSPND — USB Suspend Flag
To save power, this read/write bit should be set by the software if a 3ms con-
stant idle state is detected on USB bus. Setting this bit stops the clock to the
USB and causes the USB module to enter Suspend mode. Unnecessary ana-
log circuitry will be powered down. Software must clear this bit after the
Resume ag (RESUMF) is set while this Resume interrupt ag is serviced.
TXD0IE — Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt
when the TXD0F bit becomes set.
1 =
USB interrupts enabled for Transmit Endpoint 0.
0 =
USB interrupts disabled for Transmit Endpoint 0.
RXD0IE — Endpoint 0 Receive Interrupt Enable
This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt
when the RXD0F bit becomes set.
1 =
USB interrupts enabled for Receive Endpoint 0.
0 =
USB interrupts disabled for Receive Endpoint 0.
TXD0FR — Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.Writing a
logic 0 to TXD0FR has no effect. Reset clears this bit.
RXD0FR — Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.Writing a
logic 0 to RXD0FR has no effect. Reset clears this bit.
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