參數(shù)資料
型號: MC68HC05JB3JP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 93/148頁
文件大?。?/td> 1600K
代理商: MC68HC05JB3JP
November 5, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05JB3
INPUT/OUTPUT PORTS
MOTOROLA
REV 1
7-3
7.1.5 PA0-PA7 Optical Interface
Port-A is programmable to use as ports for the optical interface.
See OPTICAL INTERFACE section for details.
7.2
PORT-B
Port-B is a 7-bit bi-directional port. The Port-B data register is at $0001 and the
data direction register (DDRB) is at $0005. Reset does not affect the data regis-
ters, but clears the data direction registers, thereby returning the port pins to
inputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode.
PB4-PB7 are only available on the 28-pin version of the device.
All Port-B pins have programmable pull-down or pull-up resistors. PB1 and PB2
each has 25mA current sink capability.
PB0 is also used as the 16-timer TCAP input pin. When congured as output, the
input to the input capture will be permanently tied “l(fā)ow” and no input capture can
be generated.
The table below summarizes the pin congurations for Port-B.
7.2.1 Port-B Data Register
7.2.2 Port-B Data Direction Register
DDRBx — PBx Data Direction
1 =
Port pin set as output.
0 =
Port pin set as input.
PDRBx/PURBx
DDRBx
Pin Configuration
00
PB0, PB4-PB7: Input with pull-down
PB1, PB2: Input with pull-up
01
PB0, PB4-PB7: Output Push-Pull
PB1, PB2: Output Open-drain with pull-up
1
0
Input
11
PB0, PB4-PB7: Output Push-Pull
PB1, PB2: Output Open-drain
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PORTB
R
PB7
PB6
PB5
PB4
0
PB2
PB1
PB0
$0001
W
reset:
00000000
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DDRB
R
DDRB7
DDRB6
DDRB5
DDRB4
SLOWE
DDRB2
DDRB1
DDRB0
$0005
W
reset:
00000000
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