參數(shù)資料
型號: MC68HC05JB3JP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 95/148頁
文件大?。?/td> 1600K
代理商: MC68HC05JB3JP
GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
INPUT/OUTPUT PORTS
MC68HC05JB3
7-4
REV 1
SLOWE — Slow Transition Enable
See Section 7.2.4 for details.
1 =
Enable slow falling-edge output transition feature on PB1 and PB2.
0 =
Disable slow falling-edge output transition feature on PB1 and PB2.
7.2.3 Port-B Pull-down/up Register
With the pull-up/down mask option selected, PB0 and PB4-PB7 each has an inter-
nal pull-down resistor, while PB1 and PB2 each has an internal pull-up resistor,
which can be enabled by writing a ‘0’ to the corresponding bit in the Port-B
pull-down/up control register (PDURB) at location $0011.
PDRBx — PBx Pin Pull-down enable
1 =
Internal pull-down disabled.
0 =
Internal pull-down enabled.
PURBx — PBx Pin Pull-up enable
1 =
Internal pull-up disabled.
0 =
Internal pull-up enabled.
7.2.4 PB1, PB2 Slow Transition Output
The slow transition output feature is enabled by setting the SLOWE bit in DDRB at
$0005.
PB2 — a high-to-low output transition is a sharp falling edge transition delayed by
tCYC ÷ 2.
PB1 — a high-to-low output transition is a slow falling edge (drops from 5.0V to
2.2V in 167ns typically at fOP=3MHz, with 50pF load) followed by a fast transition
to VSS. The fast transition duration is depending on the strength of the output
driver dened for each port. See Figure 7-1.
Both PB1 and PB2 have 25mA current sink capability.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDURB
R
$0011
W
PDRB7
PDRB6
PDRB5
PDRB4
PURB2
PURB1
PDRB0
reset:
00000000
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