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參數資料
| 型號： | MC68HC05JB3JP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數： | 84/148頁 |
| 文件大?。?/td> | 1600K |
| 代理商： | MC68HC05JB3JP |
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GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
RESETS
MC68HC05JB3
5-2
REV 1
5.1
POWER-ON RESET
A positive transition on the VDD pin generates a power-on reset. The power-on
reset is strictly for conditions during powering up and cannot be used to detect
drops in power supply voltage.
A 224tCYC or 4064tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at logic zero at
the end of the multiple tCYC time, the MCU remains in the reset condition until the
signal on the RESET pin goes to a logic one.
5.2
EXTERNAL RESET
A logic zero applied to the RESET pin for 1.5tCYC generates an external reset.
This pin is connected to a Schmitt trigger input gate to provide and upper and
lower threshold voltage separated by a minimum amount of hysteresis. The exter-
nal reset occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold. This active
low input will generate the internal RST signal that resets the CPU and peripher-
als.
The RESET pin can also act as an open drain output. It will be pulled to a low
state by an internal pulldown device that is activated by three internal reset
sources. This RESET pulldown device will only be asserted for 3 to 4 cycles of the
internal clock, fOP, or as long as the internal reset source is asserted. When the
external RESET pin is asserted, the pulldown device will not be turned on.
NOTE
Do not connect the RESET pin directly to VDD, as this may overload some power
supply designs when the internal pulldown on the RESET pin activates.
5.3
INTERNAL RESETS
The ve internally generated resets are the initial power-on reset function, the
COP Watchdog timer reset, the low voltage reset, and the illegal address detector.
Only the COP Watchdog timer reset, low voltage reset and illegal address detec-
tor will also assert the pulldown device on the RESET pin for the duration of the
reset function or 3 to 4 internal clock cycles, whichever is longer.
5.3.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabi-
lize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 224 or 4064 (224 or 4064 is selected by mask option) internal processor
bus clock cycles after the oscillator becomes active.
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