參數(shù)資料
型號(hào)： MC68HC05L1FU
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁(yè)數(shù)： 21/102頁(yè)
文件大?。?/td> 632K
代理商： MC68HC05L1FU
MC68HC05L1
MOTOROLA
3-1
MEMORY AND REGISTERS
3
MEMORY AND REGISTERS
This section describes the organization of the on-chip memory.
3.1
Memory Map
The CPU can address 8K-bytes of memory space. The ROM portion of memory holds the
program instructions, xed data, user-dened vectors, and interrupt service routines. The RAM
portion of memory holds variable data. I/O registers are memory-mapped so that the CPU can
access their locations in the same way that it accesses all other memory locations. Figure 3-1
shows the Memory Map for the MC68HC05L1/
MC68HC705L1.
3.2
Input/Output Section
The rst 32 addresses of memory space, $0000-$001F, are the I/O section. These are the
addresses of the I/O control registers, status registers, and data registers. Table 3-1 shows these
registers and their respective bits.
3.3
RAM
The 128 addresses from $0080-$00FF are RAM locations. The CPU uses the 64 RAM addresses,
$00C0-$00FF, as the stack. Before processing an interrupt, the CPU uses ve bytes of the stack
to save the contents of the CPU registers. During a subroutine call, the CPU uses two bytes of the
stack to store the return address. The stack pointer decrements during pushes and increments
during pulls.
Note:
Be careful when using nested subroutines or multiple interrupt levels. The CPU may
overwrite data in the RAM during a subroutine or during the interrupt stacking
operation. Once the stack pointer passes $00C0, it wraps round back to $00FF.
TPG
23
相關(guān)PDF資料
PDF描述
MC68HC05L1B 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
MC68HC705L2B 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42
MC68HC705L2CB 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42
MC68HC05L2CB 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
MC68HC705MC4DW 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDSO28
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