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參數(shù)資料
| 型號： | MC68HC05L1FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 43/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC05L1FU |
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MC68HC05L1
MOTOROLA
5-9
PROGRAMMABLE TIMER
5
1 (set)
–
Timer Overow interrupt enabled.
0 (clear) –
Timer Overow interrupt disabled.
FOLV2 - Force Output Compare 2
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this
position will force the OLV2 bit to the corresponding output level latch, thus appearing at the
TCMP2 pin. Note that this bit does not affect the OCF2 bit of the Timer Status register.
1 (set)
–
OVL2 bit forced to output level latch.
0 (clear) –
No effect.
FOLV1 - Force Output Compare 1
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this
position will force the OLV1 bit to the corresponding output level latch, thus appearing at the
TCMP1 pin. Note that this bit does not affect the OCF1 bit of the Timer Status register.
1 (set)
–
OVL1 bit forced to output level latch.
0 (clear) –
No effect.
OLVL2 - Output Level Voltage Latch 2
When OLVL2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
1 (set)
–
High output on TCMP2 pin if counter compare 2 is true.
0 (clear) –
Low output on TCMP2 pin if counter compare 2 is true.
IEDG1 - Input Edge 1
When IEDG is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the
free-running counter value to the Input Capture register 1. When clear, a negative-going edge
triggers the transfer.
1 (set)
–
TCAP1 is positive-going edge sensitive.
0 (clear) –
TCAP1 is negative-going edge sensitive.
Note:
There is no need for an equivalent bit for the Input Capture register 2 ad TCAP2 is
negative-going edge sensitive only.
TPG
43
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