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參數(shù)資料
| 型號： | MC68HC05L1FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 82/102頁 |
| 文件大小： | 632K |
| 代理商： | MC68HC05L1FU |
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MOTOROLA
10-4
MC68HC05L1
OPERATING MODES
10
10.3
Bootstrap Mode
The bootstrap mode is provided in the EPROM part (MC68HC705L1) as a mean of
self-programming its EPROM with minimal circuitry. It is entered on the rising edge of RESET if
IRQ pin is at 1.8VDD and TCAP1 is at logic one. RESET must be held low for 4064 cycles after
POR (power-on reset).
10.3.1
EPROM Programming
The Program Control register (PCR) is provided for EPROM programming. The function of the
EPROM depends on the device operating mode. Figure 10-4 shows the EPROM programming
circuit for MC68HC705L1.
10.3.2
Program Control Register (PCR)
LATA - EPROM Latch Control
1 (set)
–
EPROM address and data bus congured for programming (writes to
EPROM cause address data to be latched). EPROM is in
programming mode and cannot be read if LATA is 1. This bit should
not be set unless a programming voltage is applied to the VPP pin.
0 (clear) –
EPROM address and data bus congured for normal reads.
Table 10-2 Self-Check Report
PA3
PA2
PA1
PA0
REMARKS
1
Bad Interrupts
1
0
Bad Timer
1
0
1
Bad ADC
1
0
Bad ROM
1
0
1
Bad Display RAM
1
0
1
0
Bad RAM
1
0
1
Bad I/O
Flashing
Good Device
All Others
Bad Device, Bad Port A, etc.
1=LED off; 0=LED on.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0E
RESERVED
LATA
EPGM
uuuu uu00
TPG
78
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