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參數(shù)資料
| 型號： | MC68HC05L1FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 53/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC05L1FU |
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MOTOROLA
6-4
MC68HC05L1
ANALOG TO DIGITAL CONVERTER
6
CH3-CH0 - Channel 3, 2, 1 and 0
These bits select the A/D channel assignment. See Table 6-2.
Note:
Using one or more pins of PC0/AN0-PC5/AN5 as analog inputs does not affect the
ability to use port C inputs as digital inputs. However, using port C for digital inputs
during an analog conversion sequence may inject noise on the analog inputs and
reduce the accuracy of the A/D result.
Performing a digital read of port C with levels other than VDD or VSS on the inputs causes greater
than normal power dissipation during the read and may give erroneous results.
6.3
ADC Result Data Register (ADDATA)
ADDATA is a read-only register which is used to store the result of an A/D conversion. The result
is loaded into the register from the successive approximation register and the conversion complete
ag in the ADC Status/Control register (COCO at address $09) is set.
Table 6-2 ADC Channel Assignment
CH3
CH2
CH1
CH0
CHANNEL SELECTED
0
AN0, port C bit 0
0
1
AN1, port C bit 1
0
1
0
AN2, port C bit 2
0
1
AN3, port C bit 3
0
1
0
AN4, port C bit 4
0
1
0
1
AN5, port C bit 5
0110
VRH pin (high)
(available in MC68HC05L1 only)
0111
(VRH + VRL) ÷ 2
1000
VRL pin (low)
(available in MC68HC05L1 only)
1001
VRL pin (low)
1010
VRL pin (low)
1011
VRL pin (low)
1100
VRL pin (low)
1101
VRL pin (low)
1110
VRL pin (low)
1111
VRL pin (low)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$08
uuuu uuuu
TPG
52
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