參數(shù)資料
型號(hào)： MC68HC05LJ5P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16
封裝： PLASTIC, DIP-16
文件頁(yè)數(shù)： 22/85頁(yè)
文件大?。?/td> 899K
代理商： MC68HC05LJ5P
November 10, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05LJ5
INTERRUPTS
MOTOROLA
REV 1
4-3
4.3
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-
cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter-
rupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is specied by the con-
tents of memory locations $0FFC and $0FFD.
4.4
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware inter-
rupts which are explained in the following sections.
4.5
EXTERNAL INTERRUPT (IRQ)
Interrupts from external pins are available on:
IRQ pin
PA0 to PA3 pins (enabled by mask option)
PA7 pin
4.5.1 IRQ, PA0, PA1, PA2, and PA3 Pins
If “edge-only” sensitivity is chosen by mask option, the IRQ interrupt is sensitive to
the following cases:
1.
Falling edge on the IRQ pin.
2.
Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).
If “edge-and-level” sensitivity is chosen, the IRQ interrupt is sensitive to the follow-
ing cases:
1.
Low level on the IRQ pin.
2.
Falling edge on the IRQ pin.
3.
High level on any PA0-PA3 pin with IRQ enabled (via mask option).
4.
Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).
The IRQE enable bit controls whether an active IRQF ag can generate an IRQ
interrupt sequence. This interrupt is serviced by the interrupt service routine
located at the address specied by the contents of $0FFA and $0FFB.
The IRQ latch is automatically cleared by entering the interrupt service routine if
IRQE1 enable bit is cleared. If IRQE1 enable bit is also set, the only way of clear-
ing IRQF is by writing a logic one to the IRQR acknowledge bit. Writing a logic one
to the IRQR acknowledge bit in the ICSR is the other way of clearing IRQF ag,
regardless of the status of the IRQE1 bit, besides IRQ vector fetch. This condi-
tional reset of IRQF ag provides a way for the user to differentiate the interrupt
sources from IRQ and IRQ1 latches and also to make it HC05J1A compatible if
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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