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參數(shù)資料
| 型號(hào)： | MC68HC05LJ5P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 29/85頁 |
| 文件大?。?/td> | 899K |
| 代理商： | MC68HC05LJ5P |
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November 10, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05LJ5
LOW POWER MODES
MOTOROLA
REV 1
6-1
SECTION 6
LOW POWER MODES
The MC68HC05LJ5 is capable of running in one of several low-power operating
modes. The WAIT and STOP instructions provide two modes that reduce the
power required for the MCU by stopping various internal clocks and/or the on-chip
oscillator. The STOP and WAIT instructions are not normally used if the COP
Watchdog Timer is enabled. A mask option is provided to convert the STOP
instruction to a HALT, which is a WAIT-like instruction that does not halt the COP
Watchdog Timer but has a recovery delay. The ow of the STOP, HALT, and WAIT
modes are shown in Figure 6-1.
6.1
STOP INSTRUCTION
The STOP instruction can result in one of two modes of operation depending on
the STOP mask option chosen. One option is for the STOP instruction to operate
like the STOP in normal MC68HC05 family members and place the device in the
STOP Mode. The other option is for the STOP instruction to behave like a WAIT
instruction (except that the restart time will involve a delay) and place the device in
the HALT Mode.
6.1.1 STOP Mode
Execution of the STOP instruction in this mode (as chosen by a mask option)
places the MCU in its lowest power consumption mode. In the STOP Mode the
internal oscillator is turned off, halting all internal processing, including the COP
Watchdog Timer.
When the CPU enters STOP Mode the interrupt ags (TOF and RTIF) and the
interrupt enable bits (TOFE and RTIE) in the TCSR are cleared by internal hard-
ware to remove any pending timer interrupt requests and to disable any further
timer interrupts. Execution of the STOP instruction automatically clears the I-bit in
the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Sta-
tus Register so that the IRQ external interrupt is enabled. All other registers,
including the other bits in the TCSR, and memory remain unaltered. All input/out-
put lines remain unchanged.
The MCU can be brought out of the STOP Mode only by an IRQ external interrupt
or an externally generated RESET or an LVR reset. When exiting the STOP Mode
the internal oscillator will resume after a 4064 internal processor clock cycle oscil-
lator stabilization delay.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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