參數(shù)資料
型號： MC68HC05LJ5P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 46/85頁
文件大?。?/td> 899K
代理商： MC68HC05LJ5P
GENERAL RELEASE SPECIFICATION
November 10, 1998
MOTOROLA
MULTI-FUNCTION TIMER
MC68HC05LJ5
8-4
REV 1
TOFR - Timer Overow Acknowledge
The TOFR is an acknowledge bit that resets the TOF ag bit. This bit is unaf-
fected by reset. Reading the TOFR will always return a logical zero.
1 =
Clears the TOF ag bit.
0 =
Does not clear the TOF ag bit.
RTIFR - Real Time Interrupt Acknowledge
The RTIFR is an acknowledge bit that resets the RTIF ag bit. This bit is unaf-
fected by reset. Reading the RTIFR will always return a logical zero.
1 =
Clears the RTIF ag bit.
0 =
Does not clear the RTIF ag bit.
RT1:RT0 - Real Time Interrupt Rate Select
The RT0 and RT1 control bits select one of four taps for the Real Time Interrupt
circuit. Table 8-1 shows the available interrupt rates for two fOP values. Both the
RT0 and RT1 control bits are set by reset, selecting the lowest periodic rate and
therefore the maximum time in which to alter these bits if necessary. Care
should be taken when altering RT0 and RT1 if the time-out period is imminent
or uncertain. If the selected tap is modied during a cycle in which the counter
is switching, an RTIF could be missed or an additional one could be generated.
To avoid problems, the COP should be cleared just prior to changing RTI taps.
8.2
COP WATCHDOG TIMER
The COP (Computer Operating Properly) Watchdog Timer function is imple-
mented on this device by using the output of the RTI circuit and further dividing it
by eight. The minimum COP reset times are listed in Table 8-1. If the COP circuit
times out, an internal reset is generated and the reset vector is fetched. Prevent-
ing a COP time-out is done by writing a logical zero to bit 0 of address $0FF0 as
shown in Figure 8-4. The COP register is shared with a Test ROM byte. This
address location is not affected by any reset signals. Reading this location will
return the Test ROM byte. When the COP is cleared, only the nal divide by eight
stage (output of the RTI) is cleared. The COP Watchdog Timer can be enabled/
disabled by a mask option.
Table 8-1. RTI and COP Rates at fOP=3.0MHz
Bus Frequency, fBUS=fOP=2.0 MHz
RT1
RT0
Divide Ratio
RTI Rate
COP Reset Period
(RTI x 8)
00
214
8.912ms
66ms
01
215
16.384ms
131ms
10
216
32.768ms
262ms
11
217
65.536ms
524ms
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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