參數(shù)資料
型號(hào)： MC68HC05LJ5P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16
封裝： PLASTIC, DIP-16
文件頁(yè)數(shù)： 50/85頁(yè)
文件大小： 899K
代理商： MC68HC05LJ5P
GENERAL RELEASE SPECIFICATION
November 10, 1998
MOTOROLA
INSTRUCTION SET
MC68HC05LJ5
9-2
REV 1
9.1.3 Direct
Direct instructions can access any of the rst 256 memory addresses with two
bytes. The rst byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
9.1.4 Extended
Extended instructions use only three bytes to access any address in memory. The
rst byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
9.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the rst 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
9.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the rst 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the rst 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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