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參數(shù)資料
| 型號(hào)： | MC68HC08LT8 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 119/156頁(yè) |
| 文件大?。?/td> | 1030K |
| 代理商： | MC68HC08LT8 |
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COP Control Register
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
119
12.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1.
(See
3.3 Configuration Register 1 (CONFIG1)
.)
12.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
12.5 Interrupts
The COP does not generate CPU interrupt requests.
12.6 Monitor Mode
When monitor mode is entered with V
TST
on the IRQ pin, the COP is disabled as long as V
TST
remains
on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having V
TST
on the IRQ pin, the COP is automatically disabled until a POR occurs.
12.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
12.7.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically
clear the COP counter in a CPU interrupt routine.
12.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available
that disables the STOP instruction. When the STOP bit in the configuration register has the STOP
instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
12.8 COP Module During Break Mode
The COP is disabled during a break interrupt when V
TST
is present on the RST pin.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 12-2. COP Control Register (COPCTL)
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