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參數(shù)資料
| 型號： | MC68HC681FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 21/88頁 |
| 文件大?。?/td> | 461K |
| 代理商： | MC68HC681FN |
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Operation
MOTOROLA
MC68HC681 USER’S MANUAL
3-5
3
3.3.1 Automatic-Echo Mode
In this mode, the channel automatically retransmits the received data on a bit-by-bit basis.
The local CPU-to-receiver communication continues normally but the CPU-to-transmitter
link is disabled.
3.3.2 Local-Loopback Mode
In this mode, the transmitter output is internally connected to the receiver input. The external
TxD pin is held in the mark (high) state in this mode. This mode is useful for testing the
operation of a local DUART channel. By sending data to the transmitter and checking that
the data assembled by the receiver is the same data that was sent, proper channel operation
can be assured. In this mode the CPU-to-transmitter and CPU-to-receiver communications
continue normally.
3.3.3 Remote-Loopback Mode
In this mode, the channel automatically retransmits the received data on a bit-by-bit basis.
The local CPU-to-receiver and CPU-to-transmitter links are disabled. This mode is useful in
testing the receiver and transmitter operation of a remote channel. This mode requires the
remote channel receiver to be enabled.
3.4 MULTIDROP MODE
Customers can program the channel to operate in a wake-up mode for multidrop
applications. This mode is selected by setting bits three and four in mode register one
(MR1). In this mode of operation, a master station’s channel, connected to several slave
stations (a maximum of 256 unique slave stations), transmits an address character followed
by a block of data characters targeted for one or more of the slave stations. In this mode,
the channel receivers within the slave stations are disabled, but they continuously monitor
the data stream sent out from the master station. When the slave station’s channel receivers
detect any address character in the data stream, each receiver notifies its respective CPU
by setting receiver ready (RxRDY) and generating an interrupt, if programmed to do so.
Each slave station CPU then compares the received address to its station address and
enables its receiver if it wants to receive the subsequent data from the master station. Slave
stations that are not addressed continue monitoring the data stream for the next address
character. An address character flags the end of one block of data and the start of another.
After receiving a block of data, the slave station’s CPU may disable the channel receiver and
re-initiate the process.
A transmitted character from the master station consists of a start bit, the programmed
number of data bits, an address/data (A/D) bit flag, and the programmed number of stop bits.
The address/data bit identifies to the slave station’s channel whether the character should
be interpreted as an address character or a data character. The character is interpreted as
an address character if the A/D bit is set to a one or interpreted as a data character if it is
set to a zero. The polarity of the transmitted address/data bit is selected by programming bit
two in mode register one (MR1) to a one for an address character and to a zero for data
characters. Customers should program the mode register prior to loading the corresponding
data or address characters into the transmit buffer (TBA or TBB).
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