參數(shù)資料
型號(hào)： MC68HC681FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 9/88頁(yè)
文件大小： 461K
代理商： MC68HC681FN
Introduction
1-6
MC68HC681 USER’S MANUAL
MOTOROLA
1
Four change-of-state detectors are associated with inputs IP0, IP1, IP2, and IP3. If a high-
to-low or low-to-high transition occurs on any of these inputs and the new level is stable for
more than 25 to 50 microseconds (best-to-worst case times), the corresponding bit in the
input port change register (IPCR) will be set. The sampling clock of the change detectors is
the X1/96 tap of the baud-rate generator (the 2400 baud tap), which is 38.4kHz if X1 is
3.6864MHz. A new input level must be sampled on two consecutive sample clocks to
produce a change detect. Also, customers can program the DUART to allow a change of
state to generate an interrupt to the CPU. The IPCR bits are cleared when the CPU reads
the register.
1.7 OUTPUT PORT
This 8-bit multipurpose output port can be used as a general-purpose output port.
Associated with the output port is an output port register (OPR). All bits of the OPR can be
individually set and reset. A bit is set by performing a write operation at the appropriate
address with the accompanying data specifying the bits to be set (one equals set and zero
equals no change). Similarly, a bit is reset by performing a write operation at another
address with the accompanying data specifying the bits to be reset (one equals reset and
zero equals no change).
The OPR stores data that is to be output at the output port pins. Unlike the input port, if a
particular bit of the OPR is set to a logic one or logic zero, the output pin will be at a low or
high level, respectively. Thus, a logic inversion occurs internal to the DUART with respect
to this register. The outputs are complements of the data contained in the OPR. Table 4-1
and Section 4 Programming and Register Descriptions provide more information on the
address location of the output port register and setting and resetting bits of this register.
Besides general-purpose outputs, the outputs can be individually assigned specific auxiliary
functions serving the communication channels. The assignment is accomplished by
appropriately programming the channel A and B mode registers (MR1A, MR1B, MR2A, and
MR2B) and the output port configuration register (OPCR). Section 4 Programming and
Register Descriptions provides more information on the mode registers and the OPCR.
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