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參數(shù)資料
| 型號(hào)： | MC68HC681FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 36/88頁(yè) |
| 文件大小： | 461K |
| 代理商： | MC68HC681FN |
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Programming and Register Descriptions
MOTOROLA
MC68HC681 USER’S MANUAL
4-11
4
BRG Set Select. Should only be changed after both channels have been reset and are
disabled.
0 = Set 1
1 = Set 2
Counter/Timer—Mode and Clock Source. Should only be altered while the C/T is not in
use (i.e., stopped if in counter mode, output and/or interrupt masked if in timer mode).
Mode
Clock Source
0 0 0
Counter
External (IP2)
0 0 1Counter
TxCA—1X Clock of Channel A Transmitter
0 1 0Counter
TxCB—1X Clock of Channel B Transmitter
0 1 1Counter
Crystal or External Clock (X1/Clk) Divided by 16
1 0 0Timer
External (IP2)
1 0 1Timer
External (IP2) Divided by 16*
1 1 0
Timer
Crystal or External Clock (X1/Clk)
1 1 1Timer
Crystal or External Clock (X1/Clk) Divided by 16
IP Change-Of-State Visible in ISR (Bits 3, 2, 1, 0)
0 = Disabled
1 = Enabled
IP Delta (Change-of-state) (Bits 7,6,5,4).
0 = No
1 = Yes
IP Level (Bits 3,2,1,0).
0 = Low
1 = High
Auxiliary Control Register (ACR)
76543210
BRG SET
SELECT
COUNTER/TIMER
IP3
CHANGE
VISIBLE IN
ISR
IP2
CHANGE
VISIBLE IN
ISR
IP1
CHANGE
VISIBLE IN
ISR
IP0
CHANGE
VISIBLE IN
ISR
Input Port Change Register (IPCR)
76543210
IP3 DELTA
IP2 DELTA
IP1 DELTA
IP0 DELTA
IP3 LEVEL
IP2 LEVEL
IP1 LEVEL
IP0 LEVEL
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