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參數(shù)資料
| 型號(hào)： | MC68HC681FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 49/88頁 |
| 文件大?。?/td> | 461K |
| 代理商： | MC68HC681FN |
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Programming and Register Descriptions
MOTOROLA
MC68HC681 USER’S MANUAL
4-23
4
4.3.15.1 INPUT PORT CHANGE STATUS - ISR[7]. This bit is a one when a change of
state has occurred at the IP0, IP1, IP2, or IP3 inputs and that event has been enabled to
cause an interrupt by the programming of ACR[3:0]. This bit is cleared when the CPU
reads the input port change register.
4.3.15.2 CHANNEL B CHANGE IN BREAK — ISR[6]. This bit (when set) indicates that
the channel B receiver has detected the beginning or the end of a break condition. It is
reset when the CPU issues a channel B reset break change interrupt command.
4.3.15.3 CHANNEL B RECEIVER READY OR FIFO FULL — ISR[5]. The function of
this bit is programmed by MR1B[6]. If programmed as receiver ready, it is a copy of the
channel B status register RxRDY bit (SRB[0]). If programmed as FIFO full, it is a copy of
the channel B status register FFULL bit (SRB[1]).
4.3.15.4 CHANNEL B TRANSMITTER READY — ISR[4]. This bit is a duplicate of the
channel B status register transmitter ready bit (SRB[2]).
4.3.15.5 COUNTER/TIMER READY — ISR[3]. In counter mode, this bit is set when the
counter reaches terminal count. In timer mode, this bit is set each time the timer output
switches from low to high (every other time that the C/T reaches terminal count). (In both
the MC68681 and the MC68HC681, a timer-start command forces the timer output high.
In the MC68681, if this caused a low-to-high transition of the timer output, this bit would
be set. This is not true in the MC68HC681.) In either mode, the bit is cleared by a C/T stop
command.
4.3.15.6 CHANNEL A CHANGE IN BREAK — ISR[2]. This bit is the channel A
equivalent of ISR[6].
4.3.15.7 CHANNEL A RECEIVER READY OR FIFO FULL — ISR[1]. This bit is the
channel A equivalent of ISR[5].
4.3.15.8 CHANNEL A TRANSMITTER READY — ISR[0]. This bit is the channel A
equivalent of ISR[4].
4.3.16 Interrupt Mask Register (IMR)
This register selects which bits in the interrupt status register can cause an interrupt
output. If a bit in the interrupt status register is a one and the corresponding bit in this
register is also a one, the IRQ output will be asserted. If the corresponding bit in this
register is a zero, the state of the bit in the interrupt status register has no effect on the
IRQ output. Note that the interrupt mask register does not mask the programmable
interrupt outputs OP7 through OP3 or the value read from the interrupt status register.
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