Programming and Register Descriptions
4-22
MC68HC681 USER’S MANUAL
MOTOROLA
4
4.3.13.2 COUNTER/TIMER MODE AND CLOCK SOURCE SELECT — ACR[6:4].
This field selects the operating mode of the counter/timer and its clock source as shown
in Table 4-4.
4.3.13.3 IP3, IP2, IP1, AND IP0 CHANGE-OF-STATE INTERRUPT ENABLE —
ACR[3:0]. These four bits are logically ANDed with IPCR[7:4], and the results are ORed
to produce ISR[7].
4.3.14 Input Port Change Register (IPCR)
4.3.14.1 IP3, IP2, IP1, AND IP0 CHANGE OF STATE - IPCR[7:4]. These bits are set at
25-50 microseconds, which occurs at their respective input pins. They are cleared when
the CPU reads the input port change register.
4.3.14.2 IP3, IP2, IP1, AND IP0 CURRENT STATE — IPCR[3:0]. These bits provide
the current state of their respective inputs. The information reflects the state of the input
pins at the time the input port change register is read.
4.3.15 Interrupt Status Register (ISR)
This register provides the status of all potential interrupt sources. The contents of this
register are logically ANDed with the contents of the interrupt mask register, and the
results are NORed to produce the IRQ output.
All active interrupt sources are visible by reading the ISR, regardless of the contents of
the interrupt mask register. Reading the ISR has no effect on any interrupt source; each
active interrupt source must be cleared in a source-specific fashion to clear the ISR. All
interrupt sources are cleared when the DUART is reset.
Table 4-5. Baud-Rate Generator Characteristics Crystal or Clock = 3.6864 MHz
NOMINAL RATE
(BAUD)
ACTUAL 16X CLOCK
(KHZ)
ERROR
(PERCENT)
NOMINAL RATE
(BAUD)
ACTUAL 16X CLOCK
(KHZ)
ERROR
(PERCENT)
50
0.8
0
1200
19.2
0
75
1.2
0
1800
28.8
0
100
1.759
-0.069
2000
32.056
0.175
134.5
2.153
0.059
2400
38.4
0
150
2.4
0
4800
76.8
0
200
3.2
0
7200
1115.2
0
300
4 8
0
9600
153.6
0
600
9.6
0
19.2k
307.2
0
1050
16.756
-0.260
38.4k
614.4
0