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參數(shù)資料
| 型號： | MC68HC681FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 71/88頁 |
| 文件大小： | 461K |
| 代理商： | MC68HC681FN |
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MC68HC2681
A-4
MC68HC681 USER’S MANUAL
MOTOROLA
A
A.2.3 Reset (RESET)
Operation is identical to the MC68HC681 RESET, except it is active high.
A.2.4 Chip-Select (CS)
This active low signal is used in conjunction with R and W to enable data transfers between
the CPU and DUART. If CS and R are both low, a read cycle occurs; if CS and W are both
low, a write cycle occurs. CS by itself does not cause any data transfer.
A.2.5 Write Strobe (W)
This active low signal is used in conjunction with CS to enable data to be written to a DUART
register. The write occurs at the rising edge of W or CS, whichever occurs first. W by itself
does not cause any data transfer.
A.2.6 Read Strobe (R)
This active low signal is used in conjunction with CS to enable data to be read from a DUART
register. The read occurs at the falling edge of R or CS, whichever occurs last. W by itself
does not cause any data transfer.
A.2.7 Parallel Input 6 (IP6)
This signal can be used as a general-purpose input or a channel B receiver external clock
input (RxCB). When the receiver uses the external clock , the received data is sampled on
the rising edge of the clock.
A.2.8 Parallel Input 2 (IP2)
This signal can be used as a general-purpose input or a counter/timer (C/T) external clock
input. This signal cannot be used as a channel B receiver external clock; IP6 provides that
functionality in the MC68HC2681.
A.3 PROGRAMMING AND REGISTER DESCRIPTION
Table A-2 describes the register addresses and address-triggered commands for the
MC68HC2681. The detailed description of each register and its function, given for the
MC68HC681 in Section 4 Programming and Register Descriptions, applies to the
MC68HC2681.
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