參數(shù)資料
型號(hào): MC68HC705G4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 116/128頁
文件大小: 290K
代理商: MC68HC705G4
Page 78
MOTOROLA
Section 8: TIMER SYSTEM
MC68HC05G3 (705G4) Specification Rev. 1.1
represented by two registers. These registers contain the high and low bytes of that
functional segment. Generally, accessing the low byte of a specific timer function allows full
control of that function; however, an access of the high byte inhibits that specific timer
function until the low byte also is accessed.
NOTE:
The I bit in the CCR should be set while manipulating both the high and
low byte registers of a specific timer function to ensure that an interrupt
does not occur.
Figure 8-2: Timer 1 Block Diagram
8.1.1
COUNTER
The key element in the programmable timer is a 16-bit, free-running counter or counter
register, preceded by a prescaler that divides the internal processor clock by four. The
prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0
MHz. The counter is incremented during the low portion of the internal bus clock. Software
can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two locations, $18-$19
(counter register) or $1A-$1B (counter alternate register). A read from only the least
significant byte (LSB) of the free-running counter ($19, $1B) receives the count value at the
Input
Capture
Register
Clock
Internal Bus
Output
Compare
Register
High
Byte
Low
Byte
$16
$17
/4
Internal
Processor
16-Bit Free
Running
Counter
Alternate
Register
8-Bit
Buffer
High
Byte
Low
Byte
$1A
$1B
$18
$19
High
Byte
Low
Byte
$14
$15
Output
Compare
Circuit
Overflow
Detect
Circuit
Edge
Detect
Circuit
Timer
Status
Reg.
ICF OCF TOF $13
ICIE
IEDG OLVL
Output
Level
Reg.
RESET
Timer
Control
Reg.
$12
Output
Level
(TCMP)
Interrupt
Circuit
TOIE
OCIE
Edge
Input
(TCAP)
D
CLK
C
Q
DDRG3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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