參數(shù)資料
型號: MC68HC705G4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 98/128頁
文件大小: 290K
代理商: MC68HC705G4
Page 61
Section 6: INPUT/OUTPUT PORTS
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
6.7
PORT G
Port G pins share the functions with several on-chip peripherals. A pin function is controlled
by the enable bit of each associated peripheral.
PG7 through PG4 are general-purpose I/O pins and PWM output pins. When the PWM is
enabled, one or more of the channels, PG7 through PG4, will be configured as a PWM
output pin regardless of the state of DDRG7 through DDRG4. The DDRG7 through DDRG4
bits determine the CPU read of the PORTG register (pin states for the input configuration
or data latch for the output configuration).
The PG3 pin shares function with the timer output pin (TCMP). When PG3 is configured as
an output, it will be tied to the TCMP and cannot be used to provide output from the data
register. The PG3 pin state always will be read by the CPU, regardless of the state of
DDRG3.
The PG2 through PG0 pins are shared with the serial peripheral interface (SPI2). When the
SPI2 is not used (SPE2 = 0), DDRG2 through DDRG0 bits control the directions of the pins,
and when the SPI2 is enabled, the pins are configured as serial clock output or input
(SCK2), serial data output (SDO2), and serial data input (SDI2). The direction of the SCK2
depends on the MSTR2 bit in the SPCR2. The DDRG2 through DDRG0 bits always affect
the CPU read of PORTG register (pin states for the input configuration or data latch for the
output configuration.)
Open drain or CMOS outputs are selected by GWOMH and GWOML bits in the WOM1
register. If the GWOMH bit is set, the P-channel drivers of output buffers of bit 7 through bit
4 are disabled (open drain). If the GWOML bit is set, the P-channel drivers of output buffers
of bit 3 through bit 0 are disabled (open drain). These open drain or CMOS output options
are effective to either the general-purpose outputs or the peripheral outputs (PWM, TCMP,
SCK2, and SDO2).
Port G has pullup resistors as an option. When the RGH or RGL bit in the RCR1 is set, the
pullup resistors are attached to the upper four bits or lower four bits of port G pins. (The
typical resistor values are to be 10 K
@ 3 V.) When a pin outputs a low level, the pullup
resistor is disconnected regardless of the states of the RGH or RGL bits.
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC705J1A 制造商:Freescale Semiconductor 功能描述:
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MC68HC705J1ACP 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C,IrDA,LIN,SPI,UART/USART 外圍設(shè)備:DMA,PDR,POR,PVD,PWM,溫度傳感器,WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB(64K x 8) 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN,36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND
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MC68HC705J2CDW 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MicroController, 8-Bit, 20 Pin, Plastic, SOP