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參數(shù)資料
| 型號： | MC68HC705G4 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 117/128頁 |
| 文件大小： | 290K |
| 代理商： | MC68HC705G4 |
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Page 79
Section 8: TIMER SYSTEM
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
time of the read. If a read of the free-running counter or counter alternate register first
addresses the most significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to
a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the
MSB several times. This buffer is accessed when reading the free-running counter or
counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter alternate register,
if the MSB is read, the LSB also must be read to complete the sequence.
The counter alternate register differs from the counter register in one respect: A read of the
counter register MSB can clear the timer overflow flag (TOF). Therefore, the counter
alternate register can be read at any time without the possibility of missing timer overflow
interrupts due to clearing of the TOF.
The free-running counter is configured to $FFFC during reset and always is a read-only
register. During a power-on reset, the counter is also preset to $FFFC and begins running
after the oscillator start-up delay. Because the free-running counter is 16 bits preceded by
a fixed divided-by-four prescaler, the value in the free-running counter repeats every
262,144 internal bus clock cycles. When the counter rolls over from $FFFF to $0000, the
TOF bit is set. An interrupt also can be enabled when counter rollover occurs by setting its
interrupt enable bit (TOIE).
8.1.2
OUTPUT COMPARE REGISTER
The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB)
and $17 (LSB). The output compare register is used for several purposes, such as
indicating when a period of time has elapsed. All bits are readable and writable and are not
altered by the timer hardware or reset. If the compare function is not needed, the two bytes
of the output compare register can be used as storage locations.
The output compare register contents are compared with the contents of the free-running
counter continually, and, if a match is found, the corresponding output compare flag (OCF)
bit is set and the corresponding output level (OLVL) bit is clocked to an output level register.
The output compare register values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt also can
accompany a successful output compare provided the corresponding interrupt enable bit
(OCIE) is set.
After a processor write cycle to the output compare register containing the MSB ($16), the
output compare function is inhibited until the LSB ($17) also is written. The user must write
both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not
inhibit the compare function. The free-running counter is updated every four internal bus
clock cycles. The minimum time required to update the output compare register is a
function of the program rather than the internal hardware.
The processor can write to either byte of the output compare register without affecting the
other byte. The output level (OLVL) bit is clocked to the output level register regardless of
whether the output compare flag (OCF) is set or clear. A valid output compare must occur
before the OLVL bit becomes available at the output compare pin (TCMP) with DDRG3 set.
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| MC68HC705J1A | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC705J1ACDW | 功能描述:IC MCU 4MHZ 1.2K OTP 20-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC705J1ACP | 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC705J1ACPE | 功能描述:8位微控制器 -MCU HCO5 CORE+1.2K RAM + EPR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC705J2CDW | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MicroController, 8-Bit, 20 Pin, Plastic, SOP |
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