參數(shù)資料
型號: MC68HC705G4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 76/128頁
文件大?。?/td> 290K
代理商: MC68HC705G4
Page 41
Section 4: CPU CORE
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
4.3.5
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective address of the argument is
contained in the 8-bit index register. This addressing mode can access the first 256
memory locations ($0000-$00FF). These instructions are only one byte long. This mode is
often used to move a pointer through a table or to hold the address of a frequently
referenced RAM or I/O location.
4.3.6
INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the unsigned byte following the opcode.
The addressing mode is useful for selecting the K
th element in an n element table. With this
2-byte instruction, K typically would be in X with the address of the beginning of the table
in the instruction. As such, tables may begin anywhere within the first 256 addressable
locations and could extend as far as location 510 ($01FE). This is the last location which
can be accessed in this way.
4.3.7
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the
contents of the unsigned 8-bit index register and the two unsigned bytes following the
opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except
that this 3-byte instruction allows tables to be anywhere in memory. As with direct and
extended addressing, the Motorola assembler determines the shortest form of indexed
addressing.
4.3.8
BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and
the byte following the opcode specifies the direct addressing of the byte in which the
specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory,
including I/O, can be selectively set or cleared with a single 2-byte instruction.
4.3.9
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit that is to be tested and its condition (set or clear) is included in the
opcode. The address of the byte to be tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third byte is added to the PC if the
specified bit is set or cleared in the specified memory location. This single 3-byte instruction
allows the program to branch based on the condition of any readable bit in the first 256
locations of memory. The span of branching is from -128 to +127 from the address of the
next opcode. The state of the tested bit also is transferred to the carry bit of the condition
code register.
4.3.10
INHERENT
In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations specifying only the index register and/or accumulator
as well as the control instruction with no other arguments are included in this mode. These
instructions are one byte long.
相關(guān)PDF資料
PDF描述
MC68HC05G3 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
MC68HC705J5ACJP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP16
MC68HC705J5ACP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20
MC68HC05J5AJDW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
MC68HRC705J5ACDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC705J1A 制造商:Freescale Semiconductor 功能描述:
MC68HC705J1ACDW 功能描述:IC MCU 4MHZ 1.2K OTP 20-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標準包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C,IrDA,LIN,SPI,UART/USART 外圍設(shè)備:DMA,PDR,POR,PVD,PWM,溫度傳感器,WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB(64K x 8) 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN,36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND
MC68HC705J1ACP 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標準包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C,IrDA,LIN,SPI,UART/USART 外圍設(shè)備:DMA,PDR,POR,PVD,PWM,溫度傳感器,WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB(64K x 8) 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN,36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND
MC68HC705J1ACPE 功能描述:8位微控制器 -MCU HCO5 CORE+1.2K RAM + EPR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC68HC705J2CDW 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MicroController, 8-Bit, 20 Pin, Plastic, SOP