參數(shù)資料
型號(hào): MC68HC705G4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 99/128頁
文件大?。?/td> 290K
代理商: MC68HC705G4
Page 62
MOTOROLA
Section 6: INPUT/OUTPUT PORTS
MC68HC05G3 (705G4) Specification Rev. 1.1
6.7.1
PORT G DATA REGISTER (PORTG)
READ:
anytime
(returns pin level if DDR set to input; returns output data latch if DDR set to
output; except for PG3, always return pin level regardless of the state of
DDRG3)
WRITE:
anytime
(data stored in an internal latch; drives pin only if DDR set for output
writes do not change pin state when pin configured for TCMP, SDO2, SCK2,
and PWMs peripheral output for TCMP,SDO2, SCK2, and PWMs)
RESET:
becomes high impedance inputs
6.7.2
PORT G DATA DIRECTION REGISTER (DDRG)
READ:
anytime (when OPTM = 1)
WRITE:
anytime (when OPTM = 1)
RESET:
cleared to $00 (all general-purpose I/O configured for input) DDRG
x
Port G Data Direction Register Bit
x
0 - configure I/O pin PG
x to input
1 - configure I/O pin PG
x to output
The PWM and SPI2 force the I/O state to be an output for each port G line
associated with an enabled output function such as SDO2 and PWMs. In this
case, the data direction bits will not change. When DDRG3 configures PG3 as
an output, it will be tied to the TCMP and cannot be used to provide output from
the data register.
PG7
$0006
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PORTG
B7
B6
B5
B4
B3
B2
B1
B0
UUUUUUUU
RESET:
DDRG7
option
map
$0006
DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0
DDRG
B7
B6
B5
B4
B3
B2
B1
B0
00000000
RESET:
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PDF描述
MC68HC05G3 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC705J1A 制造商:Freescale Semiconductor 功能描述:
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MC68HC705J2CDW 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MicroController, 8-Bit, 20 Pin, Plastic, SOP