參數(shù)資料
型號(hào)： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 125/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
CLOCK DISTRIBUTION
MC68HC05PD6
8-2
REV 1.1
The 7 bit divider and POR counter are initialized to $0078 by the following
conditions.
Power on detection
When FOSCE bit is cleared
8.2
SYSTEM CLOCK CONTROL
The system clock is provided for all internal modules except Time Base.
Both OSC and XOSC are available as the system clock source. The divide ratio is
selected by the SYS1 and SYS0 bits in the MISC register. By default OSC divided
by 64 is selected on reset.
8.3
OSC AND XOSC
The secondary oscillator (XOSC) runs continuously after Power-Up. The main
oscillator (OSC) can be stopped to conserve power via the STOP instruction or
the FOSCE bit in the MISC register. The effects of restarting the OSC will vary
depending on current state of the MCU, including SYS0:1 and FOSCE.
8.3.1 OSC On Line
If the system clock is OSC, FOSCE should remain 1. Executing the STOP
instruction in this condition will halt OSC, put the MCU into a low power mode and
clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with
external IRQ or Reset re-starts the oscillator. When the POR counter overows,
internal Reset is released and execution can begin. The stabilization time will vary
between 7944 and 8072 counts.
NOTE
Exiting STOP with external Reset will always return the MCU to the
state as dened by the register denitions. i.e. SYS0:1=1:0,
FOSCE=1.
Table 8-1. System Clock Frequencies
SYS1
SYS0
DIVIDE RATIO
OSC=4MHz
OSC=4.1943MHz
XOSC=76.8kHz
0
OSC
÷ 2
2MHz
2.0972MHz
—
0
1
OSC
÷ 4
1MHz
1.0486MHz
—
1
0
OSC
÷ 64
62.5kHz
65.536kHz
—
1
XOSC
÷ 4
—
19.2kHz
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