參數(shù)資料
型號： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 136/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
CLOCK DISTRIBUTION
MC68HC05PD6
8-12
REV 1.1
STUP – XOSC Time Up Flag
The power on detection clears this bit. This bit is set after the Time Base has
counted 8072 clocks. An reset does not affect this bit.
0 =
XOSC is not stabilized or no signal on XOSC1-XOSC2 pins
1 =
XOSC clock is available for the system clock
SYS1, SYS0 – System Clock Select
These two bits select the system clock source for all internal modules except
Time Base. On reset the SYS1 and SYS0 bits are initialized to 1 and 0,
respectively.
FOSCE - Fast (Main) Oscillator Enable
The FOSCE bit controls the main oscillator activity. This bit should not be
cleared by the CPU when the main oscillator is selected as the system clock
source.
0 =
OSC is shut down; 7 bit divider at the OSC input and POR counter
are initialized to $0078; FTUP ag is cleared.
1 =
Main oscillator starts again; FTUP ag is set by the POR counter
overow (8072 clocks).
OPTM - Option Map Select
The OPTM bit selects one of two register maps at $0000-$003F. This bit is
cleared on reset.
0 =
Main register map is selected
1 =
Option map is selected
SYS1
SYS0
DIVIDE RATIO
OSC=4MHz
OSC=4.1943MHz
XOSC=76.8kHz
0
OSC
÷ 2
2MHz
2.0972MHz
—
0
1
OSC
÷ 4
1MHz
1.0486MHz
—
1
0
OSC
÷ 64
62.5kHz
65.536kHz
—
1
XOSC
÷ 4
—
19.2kHz
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