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| 型號： | MC68HC705PD6 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 98/165頁 |
| 文件大?。?/td> | 841K |
| 代理商： | MC68HC705PD6 |
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GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
INTERRUPTS
MC68HC05PD6
4-4
REV 1.1
SWI instruction executes after interrupts which were pending before the SWI was fetched,
or before interrupts generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of $FFFC and $FFFD.
4.4
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is
set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables
the hardware interrupts. There are four types of hardware interrupts which are explained
in the following sections.
4.4.1 P-Decoder Interrupt (PDI)
The P-Decoder interrupt vectors located at $FFFA and $FFFB. It contains four interrupt
sources (DCI, DBI, MSGI, ADRI). These interrupts are generated only if the
corresponding enable bit is set and the I bit of the CCR is cleared. See Section 12 for
more information on P-Decoder interrupts.
4.4.2 IRQ1 and IRQ2
Two external interrupt request inputs, IRQ1 and IRQ2 share the same vector address at
$FFF8 and $FFF9.
If the IRQ option is edge and level sensitive triggering (IRQ
xS=0), a low level at the IRQ
pin and a cleared interrupt mask bit of the condition code register will cause an
EXTERNAL INTERRUPT to occur. If the MCU has finished with the interrupt service
routine, but the IRQ pin is still low, the EXTERNAL INTERRUPT will start again. In fact,
the MCU will keep on servicing the EXTERNAL INTERRUPT as long as the IRQ pin is
low. If the IRQ pin goes low for a while and resumes to high (a negative pulse) before the
interrupt mask bit is cleared, the MCU will not recognize there was an interrupt request,
and no interrupt will occur after the interrupt mask bit is cleared. IRQ
xS is located in
Interrupt Control Register (INTCR).
If the IRQ option is negative edge sensitive triggering (IRQ
xS=1), a negative edge occurs
at the IRQ pin and a cleared interrupt mask bit of the condition code register will cause an
EXTERNAL INTERRUPT to occur. If the MCU has finished with the interrupt service
routine, but the IRQ pin has not returned back to high, no further interrupt will be
generated. The interrupt logic recognizes negative edge transitions and pulses (special
case of negative edges) only. If the negative edge occurs while the interrupt mask bit is
set, the interrupt signal will be latched, and interrupt will occur as soon as the interrupt
mask bit is cleared. The latch will be cleared by RESET or cleared automatically during
fetch of the EXTERNAL INTERRUPT vectors. Therefore, one (and only one) external
interrupt edge could be latched while the interrupt mask bit is set.
The IRQ1 and IRQ2 are enabled by IRQ1E and IRQ2E bits and IRQ1F and IRQ2F bits
are provided as an indicator in the Interrupt Status Register (INTSR). Since the IRQ1(2)F
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