參數(shù)資料
型號： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 22/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
P-DECODER
MC68HC05PD6
12-2
REV 1.1
12.2.2 Batch Structure
Codewords are structured in batches which comprise a synchronization codeword
followed by 8 frames with each frame containing 2 codewords. The frames are
numbered 0 to 7 and the pager population is divided into 8 groups. Thus each
pager is allocated to one of the 8 frames according to the 3 least signicant bits
(LSB) of its 21 bit identity, i.e. 000 = frame 0, 111 = frame 7, and only examines
address codewords in that frame. Therefore each pager’s address codewords
must only be transmitted in the frame that is allocated to it.
Message codewords for any pager may be transmitted in any frame but will follow,
directly, the associated address codeword. A message may consist of any number
of codewords transmitted consecutively and may span one or more batches.
Figure 12-1. CCIR Radiopaging Code No.1 Format
Preamble
First Batch
Second and
subsequent batc
SC: Synchronization Codeword
During at least 576 bits
= 1 batch + 1 codeword
bit reversals 10101,etc.
SC
1 Frame = 2 codewords
18 address bits
2 function bits
10 BCH check bits
P
0
Address codeword
20 message bits
10 BCH check bits
P
1
Message codeword
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