參數(shù)資料
型號(hào)： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 129/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
CLOCK DISTRIBUTION
MC68HC05PD6
8-6
REV 1.1
The COP uses the clock that is selected by the RTR1 and RTR0 bits. COP time-
out reset will be generated if the COP enable (COPE) bit is set. The COP time-out
reset has the same vector address as POR and external RESET. To prevent the
COP time-out the COP divider is cleared by writing a ‘0’ to bit 0 of address $FFF0.
When the Time Base divider is driven by the OSC clock, clock for the divider is
suspended during STOP mode or when FOSCE is 0. This may cause COP period
stretching or no COP time-out reset when processing errors occur. It is
recommended that XOSC clock to be used for the COP functions to avoid these
problems.
When the Time Base (COP) divider is driven by the XOSC clock, the divider does
not stop counting and writing a ‘0’ to bit 0 of address $FFF0 must be triggered to
prevent the COP time-out.
8.4.4 Time Base Control Register 1 (TBCR1)
TBCLK – Time Base Clock
The TBCLK bit selects Time Base clock source. This bit is cleared on reset.
After reset, write to this bit is allowed only once.
0 =
XOSC clock is selected
1 =
OSC clock divide-by 128 is selected
LCLK – LCD Clock
The LCLK bit selects clock for the LCD driver. This bit is cleared on reset.
0 =
Divide by 64 is selected
1 =
Divide by 128 is selected
Table 8-3. COP Time Out Period
RTR1
RTR0
COP PERIOD (ms)
OSC=4MHz
OSC=4.1943MHz
XOSC=76.8kHz
MIN
MAX
MIN
MAX
MIN
MAX
0
1
12.3
16.4
11.7
15.6
10
13.33
0
1
393
524
375
500
320
426.67
1
0
786
1048
750
1000
640
853.33
1
1573
2097
1500
2000
1280
1706.66
W
R
TBCR1
$0010
reset
TBCLK
0
7
00
54
0
0000
6
3210
0
LCLK
0
T2R0
T2R1
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