參數(shù)資料
型號： MC68HC705PD6
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 134/165頁
文件大?。?/td> 841K
代理商： MC68HC705PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
CLOCK DISTRIBUTION
MC68HC05PD6
8-10
REV 1.1
ALF
When this bit is set, alarm interrupt has occurred. After serving this interrupt, it
is the user’s responsibility to clear this bit, otherwise the CPU will keep on
serving this alarm interrupt when a new RTC interrupt occurs (even there is no
alarm interrupt occurs). This bit is cleared by writing a 1 to it.
SECF
When this bit is set, real time clock interrupts CPU once a second. After serving
this interrupt, it is the user’s responsibility to clear this bit, otherwise the CPU
will keep on serving this once a second interrupt when a new RTC interrupt
occurs (even there is no once a second interrupt occurs). This bit is cleared by
writing a 1 to it.
8.5.4 RTC Control Register
There are three interrupts associated with the RTC, their ags are in the RTC
Status register ($39), and their respective enable bits are the RTC Control register
($3A).
RTCE
1 =
Real time clock once a day interrupt enabled
0 =
Real time clock once a day interrupt disabled
ALE
1 =
Alarm interrupt enabled
0 =
Alarm interrupt disabled
SECE
1 =
Real time clock once a second interrupt enabled
0 =
Real time clock once a second interrupt disabled
It should be noted that the ags in the interrupt status register will be set if the
corresponding event is detected, irrespective of the setting of the interrupt enable
bits.
Following is an example showing how to use the RTC interrupt:
W
R
reset
0
7
00
54
0
0000
6
3210
0
SECE
RTCE
ALE
RTCC
$003A
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