參數(shù)資料
型號(hào)： MC68HC916X1
廠商： Motorola, Inc.
英文描述： 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述： 16位微控制器模塊（16位模塊化微控制器）
文件頁數(shù)： 146/172頁
文件大?。?/td> 1035K
代理商： MC68HC916X1
MOTOROLA
146
MC68HC916X1
MC68HC916X1TS/D
1. All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
2. The base configuration of the MC68HC916X1 requires a 4.194 MHz crystal reference.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum al-
lowable t
Xcyc
period is reduced when the duty cycle of the external clock varies. The relationship between external
clock input duty cycle and minimum t
Xcyc
is expressed:
Minimum t
Xcyc
period = minimum t
XCHL
/ (50% – external clock input duty cycle tolerance).
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during
reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high
during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference
signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
31
33
35
DSACK1 Asserted to Data In Valid
9
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted
10
t
DADI
t
CLBAN
t
BRAGA
t
GAGN
t
GH
t
GA
t
RWA
t
RWAS
—
—
50
29
—
ns
ns
t
cyc
t
cyc
t
cyc
t
cyc
ns
ns
1
37
BGACK Asserted to BG Negated
1
2
39
BG Width Negated
2
—
39A
BG Width Asserted
1
—
46
46A
47A
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
BR, BGACK, DSACK1, BERR
Asynchronous Input Hold Time
DSACK1 Asserted to BERR Asserted
11
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
BKPT Input Hold Time
150
90
—
—
t
AIST
5
—
ns
47B
48
53
54
55
70
71
72
73
74
75
t
AIHT
t
DABA
t
DOCH
t
CHDH
t
RADC
t
SCLDD
t
SCLDS
t
SCLDH
t
BKST
t
BKHT
t
MSS
t
MSH
t
RSTA
t
RSTR
t
CHP1A
t
CHP2A
15
—
0
—
40
0
15
10
15
10
—
30
—
28
—
29
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
cyc
ns
t
cyc
t
cyc
ns
ns
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
20
76
77
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
RESET Assertion Time
12
RESET Rise Time
13
CLKOUT High to Phase 1 Asserted
14
0
—
—
4
78
—
10
100
101
3
40
40
CLKOUT High to Phase 2 Asserted
14
3
102
Phase 1 Valid to AS or DS Asserted
14
t
P1VSA
10
—
ns
103
Phase 2 Valid to AS or DS Asserted
14
t
P2VSN
10
—
ns
104
AS or DS Valid to Phase 1 Negated
14
t
SAP1N
10
—
ns
105
AS or DS Negated to Phase 2 Negated
14
t
SNP2N
10
—
ns
Table 78 AC Timing (Continued)
(V
DD
and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
1
Num
Characteristic
Symbol
Min
Max
Unit
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