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參數(shù)資料
| 型號： | MC68HC916X1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Modular Microcontroller(16位模塊化微控制器) |
| 中文描述： | 16位微控制器模塊（16位模塊化微控制器） |
| 文件頁數(shù)： | 54/172頁 |
| 文件大小： | 1035K |
| 代理商： | MC68HC916X1 |
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MOTOROLA
54
MC68HC916X1
MC68HC916X1TS/D
4.5 Addressing Modes
The CPU16 provides ten types of addressing. Each type encompasses one or more addressing
modes. Six CPU16 addressing types are identical to M68HC11 addressing types.
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an extension
field to form a 20-bit effective address. Extension fields are part of a bank switching scheme that
provides the CPU16 with a 1 Mbyte address space. Bank switching is transparent to most instruc-
tions. ADDR[19:16] of the effective address change when an access crosses a bank boundary.
However, it is important to note that the value of the associated extension field is dependent on the
type of instruction, and usually does not change as a result of effective address calculation.
In the immediate modes, the instruction argument is contained in bytes or words immediately fol-
lowing the instruction. The effective address is the address of the byte following the instruction. The
AIS, AIX/Y/Z, ADDD and ADDE instructions have an extended 8-bit mode where the immediate val-
ue is an 8-bit signed number that is sign-extended to 16 bits, and then added to the appropriate
register. Use of the extended 8-bit mode decreases execution time.
Extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective ad-
dress is formed by concatenating EK and the 16-bit extension.
In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are
used to calculate the effective address. Signed 16-bit mode and signed 20-bit mode are extensions
to the M68HC11 indexed addressing mode.
For 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value
contained in the index register and its associated extension field.
For 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained
in the index register and its associated extension field.
For 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. This
mode is used for JMP and JSR instructions.
Inherent mode instructions use information available to the processor to determine the effective ad-
dress. Operands (if any) are system resources and are thus not fetched from memory.
Accumulator offset mode adds the contents of 16-bit accumulator E to one of the index registers
and its associated extension field to form the effective address. This mode allows use of index reg-
isters and an accumulator within loops without corrupting accumulator D.
Relative modes are used for branch and long branch instructions. A byte or word signed two's com-
plement offset is added to the program counter if the branch condition is satisfied. The new PC val-
ue, concatenated with the PK field, is the effective address.
Post-modified index mode is used with the MOVB and MOVW instructions. A signed 8-bit offset is
added to index register X after the effective address formed by XK and IX is used.
In M68HC11 systems, direct mode can be used to perform rapid accesses to RAM or I/O mapped
into page 0 ($0000 to $00FF), but the CPU16 uses the first 512 bytes of page 0 for exception vec-
tors. To compensate for the loss of direct mode, the ZK field and index register Z have been as-
signed reset initialization vectors. By resetting the ZK field to a chosen page, and using 8-bit
unsigned index mode with IZ, a programmer can access useful data structures anywhere in the ad-
dress map.
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| MC68HC98LJ12CFUE | 功能描述:8位微控制器 -MCU 8 BIT MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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