參數(shù)資料
型號(hào): MC68HC916X1
廠商: Motorola, Inc.
英文描述: 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述: 16位微控制器模塊(16位模塊化微控制器)
文件頁數(shù): 31/172頁
文件大?。?/td> 1035K
代理商: MC68HC916X1
MC68HC916X1
MC68HC916X1TS/D
MOTOROLA
31
Figure 9 Operand Byte Order
3.6.8 Operand Alignment
The data multiplexer establishes the necessary connections for different combinations of address
and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their re-
quired positions. Positioning of bytes is determined by the size and address outputs.
SIZ1 and SIZ0 indicate the remaining number of bytes to be transferred during the current bus cy-
cle. The number of bytes transferred is equal to or less than the size indicated by SIZ1 and SIZ0,
depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1]
indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates
the byte offset from the base. Bear in mind the fact that ADDR[23:20] are driven to the same logic
state as ADDR19.
3.6.9 Misaligned Operands
CPU16 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when
it overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even
address), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the
address is on a byte boundary only. A byte operand is aligned at any address; a word or long-word
operand is misaligned at an odd address.
The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the
MCU transfers a long-word operand via a 16-bit port, the most significant operand word is trans-
ferred on the first bus cycle and the least significant operand word on a following bus cycle.
The CPU16 can perform misaligned word transfers. This capability makes it software compatible
with the M68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word
transfers.
3.6.10 Operand Transfer Cases
Table 19
shows how operands are aligned for various types of transfers. OPn entries are portions
of a requested operand that are read or written during a bus cycle and are defined by SIZ1, SIZ0,
and ADDR0 for that bus cycle.
Operand
Byte Order
16 15
OP1
OP0
31
24 23
8
7
0
Long Word
Three Byte
Word
Byte
OP0
OP2
OP1
OP0
OP3
OP2
OP1
OP0
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