參數(shù)資料
型號(hào)： MC68HC916X1
廠商： Motorola, Inc.
英文描述： 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述： 16位微控制器模塊（16位模塊化微控制器）
文件頁數(shù)： 96/172頁
文件大?。?/td> 1035K
代理商： MC68HC916X1
MOTOROLA
96
MC68HC916X1
MC68HC916X1TS/D
TIC[1:3]
— Input Capture Registers 1–3
The input capture registers are 16-bit read-only registers which are used to latch the value of TCNT
when a specified transition is detected on the corresponding input capture pin. They are reset to $FFFF.
$YFF90E, $YFF910, $YFF912
TOC[1:4]
— Output Compare Registers 1–4
The output compare registers are 16-bit read/write registers which can be used as output waveform
controls or as elapsed time indicators. For output compare functions, they are written to a desired match
value and compared against TCNT to control specified pin actions. They are reset to $FFFF.
$YFF914, $YFF916, $YFF918, $YFF91A
TI4/O5
— Input Capture 4/Output Compare 5 Register
This register serves either as input capture register 4 or output compare register 5, depending on the
state of I4/O5 in PACTL.
$YFF91C
TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of in-
put capture to be performed.
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
Each pair of bits specifies an action to be taken when output comparison is successful. Refer to
Table
48
.
EDG[4:1]B/A — Input Capture Edge Control Bits
Each pair of bits configures input sensing logic for the corresponding input capture. Refer to
Table 49
.
TCTL1/TCTL2
— Timer Control Registers 1–2
$YFF91E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 48 OM/OL[5:2] Bit Field Effects
OM/OL[5:2]
00
01
10
11
Action Taken
Timer disconnected from output logic
Toggle OCx output line
Clear OCx output line to 0
Set OCx output line to 1
Table 49 EDG[4:1]B/A Bit Field Effects
EDG[4:1]B/A
00
01
10
11
Configuration
Capture disabled
Capture on rising edge only
Capture on falling edge only
Capture on any (rising or falling) edge
TMSK1/TMSK2
— Timer Interrupt Mask Registers 1–2
$YFF920
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I4/O5I
OCI[4:1]
ICI[3:1]
TOI
0
PAOVI
PAII
CPROUT
CPR[2:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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