參數(shù)資料
型號： MC68HLC705KJ1CDWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 102/144頁
文件大?。?/td> 1377K
代理商： MC68HLC705KJ1CDWR2
Technical Data
MC68HC705KJ1 — Rev. 2.0
60
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
Rotate Byte Left through Carry Bit
— —
DIR
INH
IX1
IX
39
49
59
69
79
dd
ff
5
3
6
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
— —
DIR
INH
IX1
IX
36
46
56
66
76
dd
ff
5
3
6
5
RSP
Reset Stack Pointer
SP
← $00FF
—————
INH
9C
2
RTI
Return from Interrupt
SP
← (SP) + 1; Pull (CCR)
SP
← (SP) + 1; Pull (A)
SP
← (SP) + 1; Pull (X)
SP
← (SP) + 1; Pull (PCH)
SP
← (SP) + 1; Pull (PCL)
INH
80
9
RTS
Return from Subroutine
SP
← (SP) + 1; Pull (PCH)
SP
← (SP) + 1; Pull (PCL)
—————
INH
81
6
SBC #opr
SBC opr
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
A
← (A) – (M) – (C)
— —
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SEC
Set Carry Bit
C
← 1
———— 1
INH
99
2
SEI
Set Interrupt Mask
I
← 1
— 1 — — —
INH
9B
2
STA opr
STA opr,X
STA ,X
Store Accumulator in Memory
M
← (A)
— —
—
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
dd
hh ll
ee ff
ff
4
5
6
5
4
STOP
Stop Oscillator and Enable IRQ Pin
— 0 — — —
INH
8E
2
STX opr
STX opr,X
STX ,X
Store Index Register In Memory
M
← (X)
— —
—
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
dd
hh ll
ee ff
ff
4
5
6
5
4
SUB #opr
SUB opr
SUB opr,X
SUB ,X
Subtract Memory Byte from Accumulator
A
← (A) – (M)
— —
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Table 4-6. Instruction Set Summary (Sheet 5 of 6)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HIN Z C
C
b0
b7
b0
b7
C
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