參數(shù)資料
型號: MC68HLC705KJ1CDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 108/144頁
文件大小: 1377K
代理商: MC68HLC705KJ1CDWR2
Technical Data
MC68HC705KJ1 — Rev. 2.0
66
Resets and Interrupts
MOTOROLA
Resets and Interrupts
5.3.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $07F0.
5.3.4 Illegal Address Reset
An opcode fetch from an address not in RAM or EPROM generates a
reset.
5.4 Interrupts
The following sources can generate interrupts:
SWI instruction
External interrupt pins
IRQ/VPP pin
PA0–PA3 pins
Timer
Real-time interrupt flag (RTIF)
Timer overflow flag (TOF)
An interrupt temporarily stops the program sequence to process a
particular event. An interrupt does not stop the operation of the
instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a
user-defined interrupt vector address.
5.4.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
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