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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1CDWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 109/144頁(yè) |
| 文件大?。?/td> | 1377K |
| 代理商： | MC68HLC705KJ1CDWR2 |
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Resets and Interrupts
Interrupts
MC68HC705KJ1 — Rev. 2.0
Technical Data
MOTOROLA
Resets and Interrupts
67
5.4.2 External Interrupt
An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/VPP pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is
cleared during the return from interrupt, the CPU can recognize the new
Figure 5-4. External Interrupt Logic
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register
enables pins PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register
controls interrupt triggering sensitivity of external interrupt pins. The
IRQ/VPP pin can be negative-edge triggered only or negative-edge and
low-level triggered. Port A external interrupt pins can be positive-edge
PIRQ
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
VDD
(MOR LEVEL BIT)
RESET
IRQ VECTOR FETCH
EXTERNAL
INTERRUPT
REQUEST
(MOR)
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
IRQR
IRQE
DQ
CK
IRQ
CLR
LATCH
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