參數(shù)資料
型號: MC68HLC705KJ1CDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 106/144頁
文件大?。?/td> 1377K
代理商: MC68HLC705KJ1CDWR2
Technical Data
MC68HC705KJ1 — Rev. 2.0
64
Resets and Interrupts
MOTOROLA
Resets and Interrupts
A reset immediately stops the operation of the instruction being
executed, initializes certain control and status bits, and loads the
program counter with a user-defined reset vector address. The following
sources can generate a reset:
Power-on reset (POR) circuit
RESET pin
Computer operating properly (COP) watchdog
Illegal address
Figure 5-1. Reset Sources
5.3.1 Power-On Reset
A positive transition on the VDD pin generates a power-on reset.
NOTE:
The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064-tcyc (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If any reset source is active
at the end of this delay, the MCU remains in the reset condition until all
reset sources are inactive.
DQ
CK
S
RESET
LATCH
INTERNAL CLOCK
RST
TO CPU AND
RESET PIN
VDD
PERIPHERAL
MODULES
ILLEGAL ADDRESS
COP WATCHDOG
POWER-ON RESET
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