參數(shù)資料
型號(hào): MC68HLC705KJ1CDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁(yè)數(shù): 5/144頁(yè)
文件大小: 1377K
代理商: MC68HLC705KJ1CDWR2
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Technical Data
MC68HC705KJ1 — Rev. 2.0
102
External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
If edge- and level-sensitive triggering is selected, a rising edge or a high
level on a PA0–PA3 pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. As long as any source is holding a PA0–PA3 pin high,
an external interrupt request is latched, and the CPU continues to
execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3
pin latches an external interrupt request. A subsequent external interrupt
request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE:
The BIH and BIL instructions apply only to the level on the IRQ/VPP pin
itself and not to the output of the logic OR function with the PA0–PA3
pins. The state of the individual port A pins can be checked by reading
the appropriate port A pins as inputs.
Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether
these pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external
interrupts (PA0–PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables
all maskable interrupt requests, including external interrupt requests.
9.5 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. All unused bits in the ISCR read as logic
0s. The IRQF bit is cleared and the IRQE bit is set by reset.
Address:
$000A
Bit 7
654321
Bit 0
Read:
IRQE
0
IRQF
0
Write:
R
IRQR
Reset:
10000000
= Unimplemented
R
= Reserved
Figure 9-4. IRQ Status and Control Register (ISCR)
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