參數(shù)資料
型號： MC68MH360ZQ33LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 107/158頁
文件大小： 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
QMC Supplement
Table 2-11. CHAMR Bit Settings (Transparent Mode)
Field
Name
Description
0
MODE
Mode—Each channel has a programmable option whether to use transparent mode or HDLC
mode.
0 Transparent mode
1 HDLC mode
1
RD
Reverse data
0 The bit order will not be reversed, transmitting/receiving the LSB of each octet rst.
1 The bit order as seen on the channels is reversed, transmitting/receiving the MSB of each
octet rst.
2—
1
3
ENT
Enable transmit
0 Disable transmitter. If this bit is cleared and the channel’s transmitter is routed to a certain
time slot (within TSATTx, see Figure 2-3) the transmitter sends 1’s on this time slot.
1 The transmit portion of the channel is enabled and data is sent according to protocol and to
other control settings.
4
—
Reserved
5
SYNC
Synchronization—Controls synchronization of multichannel operation in transparent mode.
0 The rst byte is put in the rst available time slot or is read from the rst available time slot to
this logical channel.
1 The synchronization algorithm according to TRANSYNC is done.
6
RES
Reserved
7
POL
Enable polling—Enables the transmitter to poll the transmit BDs.
0 The CPM will not check the ready (R) bit in the transmit buffer descriptor.
1 The CPM will go check the ready (R) bit in the transmit buffer descriptor.
The user can use this bit to prevent unnecessary external bus cycles when checking the ready
bit (R) in the buffer descriptor. Software should always set POL at the beginning of a transmit
sequence of one or more frames. The RISC processor clears POL (0) when no more buffers are
ready in the transmit queue when it nds a buffer descriptor with the R bit cleared (0), that is, at
the end of a frame or at the end of a multiframe transmission. To prevent deadlock, software
should prepare the new BD, or multiple BDs, and set (1) the ready (R) bit in the BD before setting
(1) POL.
Note that the CPM automatically clears this bit; the user should never try to clear this bit in
software.
8–9
—
0
10–11
—
Reserved
12–15
—
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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