參數(shù)資料
型號(hào): MC68MH360ZQ33LR2
廠商: Freescale Semiconductor
文件頁數(shù): 154/158頁
文件大小: 0K
描述: IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 33MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
Chapter 6. QMC Initialization
A typical setting would be:
GSMR_H = 0x0000_0780;
/* enable pulse mode and sampling */
Step 10. Initialize general SCCx mode reg low, GSMR_L (see Table 6-5). For more
information on GSMR programming, see page 7-111 of the MC68360 User’s Manual and
page 16-153 of the MPC860 User’s Manual.
CDS
1
CD sampling
1
CTSS
1
CTS sampling
1
TFL
1
Transmit FIFO length
0
RFW
1
Receive FIFO width
0
TXSY
1
Transmitter synchronized to the receiver
0
SYNL
2
Sync length
00b
RTSM
1
RTS mode
0
RSYN
1
Receive synchronization timing
0
Table 6-5. GSMR_L Bit Settings
Name
No. of Bits
Description
Setting
SIR
1
Infrared encoding, only on 860MH
X
EDGE
2
Clock edge
00
TCI
1
Transmit clock invert
0
TSNC
2
Transmit sense
00b
RINV
1
DPLL receive input invert data
0
TINV
1
DPLL transmit input invert data
0
TPL
3
Tx preamble length
0b000
TPP
2
Tx preamble pattern
0b00
Tend
1
Transmitter frame ending
0
TDCR
2
Transmit divide clock rate
00
RDCR
2
Receive divide clock rate
00
RENC
2
Receive decoding
00
TENC
2
Transmitter decoding
00
DIAG
2
Diagnostic mode
system-specic
ENR
1
Enable receive
0
ENT
1
Enable transmit
0
MODE
4
Channel protocol mode
0b1010
Table 6-4. GSMR_H Bit Settings (Continued)
Name
No. of Bits
Description
Setting
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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