I
參數(shù)資料
型號： MC8610PX1333JB
廠商： Freescale Semiconductor
文件頁數(shù)： 35/96頁
文件大小： 0K
描述： MPU E600 CORE 1333MHZ 783-PBGA
標準包裝： 36
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.025V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應商設備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Electrical Characteristics
Freescale Semiconductor
40
2.9.2
I2C AC Electrical Specifications
Table 31 provides the AC timing parameters for the I
2C interfaces.
Input current each I/O pin (input voltage is between
0.1
× OVDD and 0.9 × OVDD(max)
II
–10
10
μA3
Capacitance for each I/O pin
CI
—10
pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the
MPC8610 Integrated Host Processor Reference Manual, for information on the digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
Table 31. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 30).
Parameter
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0400
kHz
Low period of the SCL clock
tI2CL
4
1.3
—
μs
High period of the SCL clock
tI2CH
4
0.6
—
μs
Setup time for a repeated START condition
tI2SVKH
4
0.6
—
μs
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL
4
0.6
—
μs
Data setup time
tI2DVKH
4
100
—
ns
Data input hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
02
—
μs
Data ouput delay time
tI2OVKL
—0.9 3
μs
Setup time for STOP condition
tI2PVKH
0.6
—
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1
× OVDD
—V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2
× OVDD
—V
Table 30. I2C DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
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