參數(shù)資料
型號: MC8610PX1333JB
廠商: Freescale Semiconductor
文件頁數(shù): 40/96頁
文件大?。?/td> 0K
描述: MPU E600 CORE 1333MHZ 783-PBGA
標準包裝: 36
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.333GHz
電壓: 1.025V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
45
2.12.2.2
SSI Receiver Timing with Internal Clock
Table 36 provides the receiver timing parameters with internal clock.
Figure 18 provides the SSI receiver timing with internal clock.
Figure 18. SSI Receiver with Internal Clock Timing Diagram
2.12.2.3
SSI Transmitter Timing with External Clock
Table 37 provides the transmitter timing parameters with external clock.
Table 36. SSI Receiver with Internal Clock Timing Parameters
Parameter
Symbol
Min
Max
Unit
Internal Clock Operation
(Tx/Rx) CK clock period
SS1
81.4
ns
(Tx/Rx) CK clock high period
SS2
36.0
ns
(Tx/Rx) CK clock rise time
SS3
6
ns
(Tx/Rx) CK clock low period
SS4
36.0
ns
(Tx/Rx) CK clock fall time
SS5
6
ns
(Rx) CK high to FS high
SS11
15.0
ns
(Rx) CK high to FS low
SS13
15.0
ns
SRXD setup time before (Rx) CK low
SS20
10.0
ns
SRXD hold time after (Rx) CK low
SS21
0
ns
Table 37. SSI Transmitter with External Clock Timing Parameters
Parameter
Symbol
Min
Max
Unit
External Clock Operation
(Tx/Rx) CK clock period
SS22
81.4
ns
(Tx/Rx) CK clock high period
SS23
36.0
ns
(Tx/Rx) CK clock rise time
SS24
6.0
ns
SSIn_TCK
SSIn_RFS
SSIn_RXD
SS1
SS4
SS2
SS20
SS21
SS11
SS13
(Output)
(Input)
SS3
SS5
相關(guān)PDF資料
PDF描述
345-012-523-802 CARDEDGE 12POS DUAL .100 GREEN
345-012-523-801 CARDEDGE 12POS DUAL .100 GREEN
MC8610PX1066JB MPU E600 CORE 1066MHZ 783-PBGA
345-012-523-204 CARDEDGE 12POS DUAL .100 GREEN
345-012-523-202 CARDEDGE 12POS DUAL .100 GREEN
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