參數(shù)資料
型號(hào)： MC8610PX1333JB
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 58/96頁(yè)
文件大?。?/td> 0K
描述： MPU E600 CORE 1333MHZ 783-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.025V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤(pán)
Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
61
Figure 38. Differential Measurement Points for Rise and Fall Time
Figure 39. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based on application
usage. Refer to the following sections for detailed information:
Rising edge rate (SD
n_REF_CLK) to falling edge rate
(SD
n_REF_CLK) matching
Rise-Fall
Matching
—20
%
1, 4
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 to +200 mV on the differential waveform (derived from SD
n_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 38.
4. Matching applies to rising edge rate for SD
n_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SD
n_REF_CLK rising meets SDn_REF_CLK falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge
rate of SD
n_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should
not exceed 20% of the slowest edge rate. See Figure 39.
Table 47. SerDes Reference Clock Common AC Parameters (continued)
At recommended operating conditions with X1VDD or X2VDD = 1.0 V ± 5% and 1.025 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
VIH = +200 mV
VIL = -200 mV
0.0 V
SD
n_REF_CLK
minus
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
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