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| 型號： | MC8610PX1333JB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 36/96頁 |
| 文件大小： | 0K |
| 描述： | MPU E600 CORE 1333MHZ 783-PBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.333GHz |
| 電壓： | 1.025V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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Electrical Characteristics
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
41
Figure 15 provides the AC test load for the I
2C.
Figure 15. I2C AC Test Load
Figure 16 shows the AC timing diagram for the I
2C bus.
Figure 16. I2C Bus AC Timing Diagram
Capacitive load for each bus line
Cb
—
400
pF
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I
2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. As a transmitter, the MPC8610 provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
When MPC8610 acts as the I2C bus master while transmitting, MPC8610 drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, MPC8610 would not cause unintended generation of Start or Stop condition. Therefore, the
300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required
for MPC8610 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both
the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock
frequency is 400 kHz and the digital filter sampling rate register (I2CDFSRR) is programmed with its default setting of 0x10
(decimal 16):
I2C source clock frequency
533 MHz
400 MHz
333 MHz
266 MHz
FDR bit setting
0x0A
0x07
0x2A
0x05
Actual FDR divider selected
1536
1024
896
704
Actual I2C SCL frequency generated
347 kHz
391 kHz
371 kHz
378 kHz
For the detail of I2C frequency calculation, refer to Freescale application note AN2919,
Determining the I2C Frequency
Divider Ratio for SCL. Note that the I2C source clock frequency is equal to the MPX clock frequency for MPC8610.
3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. Guaranteed by design.
Table 31. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 30).
Parameter
Symbol1
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Sr
S
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
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| 345-012-523-802 | CARDEDGE 12POS DUAL .100 GREEN |
| 345-012-523-801 | CARDEDGE 12POS DUAL .100 GREEN |
| MC8610PX1066JB | MPU E600 CORE 1066MHZ 783-PBGA |
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| 345-012-523-202 | CARDEDGE 12POS DUAL .100 GREEN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8610PX1333JZ | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8610 Integrated Host Processor Hardware Specifications |
| MC8610PX800G | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8610PX800GB | 功能描述:微處理器 - MPU REV 1.1 8610 1.0V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8610PX800GZ | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8610 Integrated Host Processor Hardware Specifications |
| MC8610PX800J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
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