參數(shù)資料
型號: MCIMX257DVM4
廠商: Freescale Semiconductor
文件頁數(shù): 10/153頁
文件大小: 0K
描述: IC MPU I.MX25 COMM 400MAPBGA
標準包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲器類型: 外部程序存儲器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
107
Note:
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on pads when SSI is being used for a data transfer.
”Tx” and “Rx” refer to the transmit and receive sections of the SSI.
For internal frame sync operation using external clock, the FS timing is the same as that of Tx Data (for example, during AC97
mode of operation).
3.7.17.3
SSI Transmitter Timing with External Clock
Figure 80 shows the timing for the SSI transmitter with external clock. Table 83 describes the timing
parameters (SS22-SS46) shown in the figure.
Figure 80. SSI Transmitter with External Clock Timing Diagram
SS48
Oversampling clock high period
6.0
ns
SS49
Oversampling clock rise time
3.0
ns
SS50
Oversampling clock low period
6.0
ns
SS51
Oversampling clock fall time
3.0
ns
Table 82. SSI Receiver Timing with Internal Clock (continued)
ID
Parameter
Min.
Max.
Unit
SS45
SS24
SS26
SS25
SS23
AUDn_TXC
AUDn_TXFS (bl)
AUDn_TXFS (wl)
AUDn_TXD
AUDn_RXD
Note: SRXD Input in Synchronous mode only
SS22
SS44
SS39
SS38
SS37
SS46
(Input)
(Output)
(Input)
SS29
SS27
SS31
SS33
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